Journal papers

  1. P. Yue, H. Zhang, R. Das, R. Harjani, and S. S. Sapatnekar, “Toward Multi-kW Power Delivery Methodologies for Advanced 3D Heterogeneous Integration,” accepted for publication in the IEEE Transactions on Components, Packaging and Manufacturing Technology, 2026.
  2. Z. Xue, R. Yin, C. Li, Z. Wang, A. Efe, S. S.  Sapatnekar, U. R. Karpuzcu, and C. H. Kim, “A coupled oscillator based ising chip as a physical entropy source for hybrid true random number generation,” Scientific Reports, 2026.
  3. C. H. Kim, P. Kreye, A. Efe, R. Yin, C. Li, A. Kumar, T. Islam, Z. Zeng, N. S. Prova, A. Vanasse, X. Li, J. Xing, Z. Wang, Z. Xue, W. Moy, H. Lo, S. S. Sapatnekar, and U. R. Karpuzcu, “COBIFIVE: A Five-Core Physics-based Ising Computing Chip,” accepted for publication in Nature Electronics, 2025.
  4. S. A. Berhan, E. Gebru, S. Ghosh, J. Poojary, S. S. Peri, J. Hu, R. Harjani, Ramprasath S., and S. S. Sapatnekar, “Automated Analog Layout Synthesis,” Journal of the Indian Institute of Science, 2026.
  5. N. S. Prova, H. Cılasun, A. Kumar, A. Efe, S. S. Sapatnekar, and U. R. Karpuzcu, “Towards Higher Order Oscillatory Ising Machines,” Scientific Reports, Vol. 16, pp. 25690:1 – 25690:11, 03 July, 2026.
  6. M. Madhusudan, J. Poojary, A. K. Sharma, Ramprasath S., K. Kunal, S. S. Sapatnekar, and R. Harjani, “Distance-Dependent Variations in FinFET CMOS and its Impact on Analog Circuits,” Vol. 61, No. 6, pp. 2951 – 2964, June 2026.
  7. Z. Zeng, A. Kumar, A. Efe, R. Yin, C. H. Kim, U. R. Karpuzcu, and S. S. Sapatnekar, “Extractive Summarization on a CMOS Ising machine,” IEEE Access, Vol. 14, pp. 56724 – 56735, 2026.
  8. Z. Zeng, A. Kumar, C. H. Kim, U. R. Karpuzcu, and S. S. Sapatnekar, “Influence Maximization under the Linear Threshold Model on a Hardware Ising Solver,” Scientific Reports, Vol. 15, pp. 43604:1 – 43604:14, 2025.
  9. S. Resch, H. Cilasun, Z. Chowdhury, M. Zabihi, Y. Lv, J.-P. Wang, S. S. Sapatnekar, I. Akturk, and U. R. Karpuzcu, “The Case for Secure Miniservers Beyond the Edge,” accepted for publication in IEEE Transactions on Computers, 2025.
  10. S. Rothe, J. Lienig, and S. S. Sapatnekar, “Temperature-aware Stress-based Migration Modeling in IC Design: Moving from Theory to Practice,” AEU – International Journal of Electronics and Communications, Vol. 200, pp. 155909:1 – 155909:9, October 2025.
  11. H. Cılasun, W. Moy, Z. Zeng, T. Islam, H. Lo, A. Vanasse, M. Tan, M. Anees, Ramprasath S., A. Kumar, S. S. Sapatnekar, C. H. Kim, U. R. Karpuzcu, “COBI: A Coupled Oscillator Based Ising Chip for Combinatorial Optimization,” Nature Electronics, 11 June 2025.
  12. M. A. A. Shohel, V. A. Chhabria, N. Evmorfopoulos, and S. S. Sapatnekar, “An Analytical Solution for Transient Electromigration Stress in Multisegment Straight-line Interconnects Based on a Stress-Wave Model,” ACM Transactions on Design Automation of Electronic Systems, Vol. 30, No. 4, pp. 57:1 – 57:31, July 2025.
  13. A. Kumar, Ramprasath S., C. H. Kim, U. R. Karpuzcu, and S. S. Sapatnekar, “DROID: Discrete-Time Simulation for Ring-Oscillator-Based Ising Design,” Scientific Reports, Vol. 15, pp. 18643:1 – 18643:16, 2025.
  14. N. Karmokar, R. Harjani, and S. S. Sapatnekar, “Minimum Unit Capacitance Calculation for Capacitor Arrays in Binary-Weighted and Split DACs,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 44, No. 4, pp. 1210 – 1223, April 2025.
  15. S. Guo, Y. Ju, X. Chen, S. S. Sapatnekar, and J. Gu, “Mobile-PBR: A 28nm Energy-Efficient Rendering Processor for Photorealistic Augmented Reality with Inverse Rendering and Background Clustering,” IEEE Journal of Solid State Circuits, Vol. 60, No. 1, pp. 125 – 135, January 2025.
  16. H. Esmaeilzadeh, S. Ghodrati, A. B. Kahng, S. Kinzer, S. D. Manasi, S. S. Sapatnekar, and Z. Wang, “Performance Analysis of DNN Inference/Training with Convolution and Non-Convolution Operations on ASIC Accelerators,” ACM Transactions on Design Automation of Electronic Systems, Vol. 30, No. 1, pp. 3:1 – 3:34, January 2025.
  17. A. K. Sharma, M. Madhusudan, S. M. Burns, S. Yaldiz, P. Mukherjee, R. Harjani, and S. S. Sapatnekar, “Constructive Place-and-Route for Transistor Arrays in Analog Circuits Under Nonlinear Gradients,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 43, No. 12, pp. 4773 – 4785, December 2024.
  18. Y. Lin, Y. Li, M. Madhusudan, S. S. Sapatnekar, R. Harjani, and J. Hu, “MMM: Machine Learning-Based Macro-Modeling for Linear Analog ICs and ADC/DACs,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 43, No. 12, pp. 4740 – 4752, December 2024.
  19. Y. Lv, B. R. Zink, R. P. Bloom, H. Cılasun, P. Khanal, S. Resch, Z. Chowdhury, A. Habiboglu, W. Wang, S. S. Sapatnekar, U. Karpuczu, and J.-P. Wang “Experimental Demonstration of Magnetic Tunnel Junction-based Computational Random-Access Memory,” npj Unconventional Computing, Vol. 1, No. 1, pp. 3:1 – 3:10, July 25, 2024.
  20. H. Esmaeilzadeh, S. Ghodrati, A. B. Kahng, J. K. Kim, S. Kinzer, S. Kundu, R. Mahapatra, S. D. Manasi, S. S. Sapatnekar, Z.Wang, and Z. Zeng, “An Open-Source ML-Based Full-Stack Optimization Framework for Machine Learning Accelerators,” ACM Transactions on Design Automation of Electronic Systems,  Vol. 29, No. 4, pp. 68:1 -- 68:33, July 2024.
  21. H. Cılasun, Z. Zeng, Ramprasath S., A. Kumar, H. Lo, W. Cho, W. Moy, C. H. Kim, U. R. Karpuzcu, and S. S. Sapatnekar, “3SAT on an All-to-All-Connected CMOS Ising Solver Chip,” Scientific Reports, Vol. 14, pp. 10757:1 – 10757:11, 2024.
  22. V. A. Chhabria, W. Jiang, A. B. Kahng, and S. S. Sapatnekar, "A Machine Learning Approach to Improving Timing Consistency between Global Route and Detailed Route," ACM Transactions on Design Automation of Electronic Systems, Vol. 29, No. 1, pp. 18:1 – 18:25, January 2024.
  23. S. Mondal, S. D. Manasi, K. Kunal, Ramprasath S., Z. Zeng, and S. S. Sapatnekar, "A Unified Engine for Accelerating GNN Weighting/Aggregation Operations, with Efficient Load Balancing and Graph-Specific Caching,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 42, No. 2, pp. 4844 – 4857, December 2023.
  24. Ramprasath S., A. K. Sharma, J. Poojary, S. Yaldiz, R. Harjani, S. M. Burns, and S. S. Sapatnekar, “A Generalized Methodology for Well Island Generation and Well-Tap Insertion in Analog/Mixed-Signal Layouts,” ACM Transactions on Design Automation of Electronic Systems, Vol. 28, No. 5, pp. 69:1 – 69:25, September 2023.
  25. K. Kunal, T. Dhar, M. Madhusudan, J. Poojary, A. K. Sharma, W. Xu, S. M. Burns, J. Hu, R. Harjani, and S. S. Sapatnekar, "GNN-based Hierarchical Annotation for Analog Circuits,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 42, No. 9, pp. 2801 – 2814, September 2023.
  26. N. Karmokar, A. K. Sharma, J. Poojary, M. Madhusudan, R. Harjani, and S. S.  Sapatnekar, “Constructive Placement and Routing for Common-Centroid Capacitor Arrays in Binary-Weighted and Split DACs,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 42, No. 9, pp. 2782 – 2795, September 2023.
  27. H. Lo, W. Moy, H. Yu, S. S. Sapatnekar, and C. H. Kim, “A 48-node All-to-all Connected Coupled Ring Oscillator Ising Solver Chip,” Nature Electronics, 31 August 2023.
  28. B. R. Zink, Y. Lv, M. Zabihi, H. Cilasun, S. S. Sapatnekar, U. R. Karpuzcu, M. D. Riedel, and J.-P. Wang, “Stochastic Computing Scheme of Embedding Random Bit Generation and Processing in Computational Random Access Memory (SC-CRAM),” IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, Vol. 9, No. 1, pp. 29 – 37, June 2023.
  29. T. Dhar, R. Harjani, and S. S. Sapatnekar, “An Aging Model for Current DACs, and its Application to Analyzing Lifetime Degradation in a Wireline Equalizer," Microelectronics Reliability, Vol. 142, pp. 114912:1 – 114912:14, March 2023.
  30. Y. Li, Y. Lin, M. Madhusudan, A. K. Sharma, S. S. Sapatnekar, R. Harjani, and J. Hu, “Performance-Driven Wire Sizing for Analog Integrated Circuits,” ACM Transactions on Design Automation of Electronic Systems, Vol. 28, No. 2, pp. 19:1 – 19:19, March 2023.
  31. V. A. Chhabria, V. Ahuja, A. Prabhu, N. Patil, P. Jain, and S. S. Sapatnekar, “Encoder-Decoder Networks for Analyzing Thermal and Power Delivery Networks,” ACM Transactions on Design Automation of Electronic Systems, Vol. 28, No. 1, pp. 3:1 – 3:27, March 2023.
  32. V. A. Chhabria and S. S. Sapatnekar, “OpeNPDN: A Neural-network-based Framework for Power Delivery Network Synthesis,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 41, No. 10, pp. 3515 – 3528, October 2022.
  33. Z. I. Chowdhury, S. K. Khatamifard, S. Resch, H. Cilasun, Z. Zhao, M. Zabihi, M. Razaviyayn, J.-P. Wang, S. S. Sapatnekar, and U. R. Karpuzcu, “CRAM-Seq: Accelerating RNA-Seq Abundance Quantification using Computational RAM,” IEEE Transactions on Emerging Topics in Computing, Vol. 10, No. 4, pp. 2055 – 2071, October 2022.
  34. S. Resch, S. K. Khatamifard, Z. I. Chowdhury, M. Zabihi, Z. Zhao, H. Cilasun, J.-P. Wang, S. S. Sapatnekar, and U. R. Karpuzcu, “Energy Efficient and Reliable Inference in Nonvolatile Memory under Extreme Operating Conditions,” ACM Transactions on Embedded Computing Systems, Vol. 21, No. 5, pp. 57:1 – 57:36, September 2022.
  35. W. Moy, I. Ahmed, P.-W. Chu, J. Moy, S. S. Sapatnekar, and C. H. Kim, “A 1,968 Coupled Ring Oscillator Combinatorial Optimization Problem Solver,” Nature Electronics, 02 May 2022.
  36. M. Zabihi, S. Resch, H. Cılasun, Z. I. Chowdhury, Z. Zhao, U. R. Karpuzcu, J.-P. Wang, and S. S. Sapatnekar “Exploring the Feasibility of Using 3D XPoint as an In-Memory Computing Accelerator,” IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, Vol. 7, No. 2, pp. 88 – 96, December 2021.
  37. L. Everson, S. S. Sapatnekar, and C. H. Kim, “A Time-Based Intra-Memory Computing Graph Processor Featuring A* Wavefront Expansion and 2D Gradient Control,” IEEE Journal of Solid-State Circuits, Vol. 56, No. 7, pp. 2281 – 2290, July 2021.
  38. F. S. Snigdha, S. D. Manasi, J. Hu, and S. S. Sapatnekar, “SeFAct2: Selective Feature Activation for Energy-Efficient CNNs using Optimized Thresholds,” in the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2020 Vol. 40, No. 8, pp. 1423 – 1436, July 2021.
  39. H. Cilasun, S. Resch, Z. I. Chowdhury, E. Olson, M. Zabihi, Z. Zhao, T. Peterson, K. K. Parhi, J. Wang, S. S. Sapatnekar, and U. R. Karpuzcu, “Spiking Neural Networks in Spintronic Computational RAM,” ACM Transactions on Architecture and Code Optimization, Vol. 18, No. 4, pp. 59:1 – 59:21, September 2021.
  40. T. Dhar, K. Kunal, Y. Li, M. Madhusudan, J. Poojary, A. K. Sharma, W. Xu, S. M. Burns, R. Harjani, J. Hu, D. A. Kirkpatrick, P. Mukherjee, S. S. Sapatnekar, and S. Yaldiz, "ALIGN: A System for Automating Analog Layout," IEEE Design & Test, Vol. 38, No. 2, pp. 8 – 18, April 2021.
  41. S. D. Manasi, F. S. Snigdha, and S. S. Sapatnekar, "NeuPart: Using Analytical Models to Drive Energy-Efficient Partitioning of CNN Computations on Cloud-Connected Mobile Clients," IEEE Transactions on VLSI Systems, Vol. 28, No. 8, pp. 1844 – 1857, August 2020.
  42. M. Zabihi, A. K. Sharma, M. G. Mankalale, Z. I. Chowdhury, Z. Zhao, S. Resch, U. R. Karpuzcu, J.-P. Wang, and S. S. Sapatnekar, “Analyzing the Effects of Interconnect Parasitics in the STT CRAM In-memory Computational Platform,”  IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, Vol. 6, No. 1, pp. 71 – 79, June 2020.
  43. Z. I. Chowdhury, M. Zabihi, S. K. Khatamifard, Z. Zhao, S. Resch, M. Razaviyayn, J.-P. Wang, S. S. Sapatnekar, and U. R.  Karpuzcu, "A DNA Read Alignment Accelerator Based on Computational RAM," IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, Vol. 6, No. 1, pp. 80 – 88, June 2020.
  44. L. Everson, S. S. Sapatnekar, and C. H. Kim, "A Shortest Path Finding Time-based Accelerator Core with Built-in Gravity Control and Buffer Zone for Smooth 3D Navigation," IEEE Solid-State Circuits Letters, Vol. 3, No. 1, pp. 66 – 69, February 2020.
  45. Q. Fan, D. J. Lilja, and S. S. Sapatnekar, "Adaptive-length Coding of Image Data for Low-cost Approximate Storage," IEEE Transactions on Computers, Vol. 69, No. 2, pp. 239 – 252, February 2020.
  46. Z. Chowdhury, S. K. Khatamifard, Z. Zhao, M. Zabihi, S. Resch, M. Razaviyayn, J.-P. Wang, S. S. Sapatnekar, and U. Karpuzcu, "Spintronic In-Memory Pattern Matching," IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, Vol. 5, No. 2, pp. 206 – 219, December 2019.
  47. S. Resch, S. K. Khatamifard, Zamshed I. Chowdhury, M.  Zabihi, Z. Zhao, J.-P. Wang, S. S. Sapatnekar, and U. R. Karpuzcu, "PIMBALL: Binary Neural Networks in Spintronic Memory," ACM Transactions on Architecture and Code Optimization, Vol. 16, Issue 4, pp. 41:1 – 41:26, October 2019.
  48. T. Li and S. S. Sapatnekar, "Stress-Induced Performance Shifts in 3D DRAMs," ACM Transactions on Design Automation of Electronic Systems, Vol. 24, No. 5, pp. 51:1 –51:21, July 2019.
  49. M. Zabihi, Z. Chowdhury, Z. Zhao, U. R. Karpuzu, J.-P. Wang, and S. S. Sapatnekar, “In-Memory Processing on the Spintronic CRAM: From Hardware Design to Application Mapping,” IEEE Transactions on Computers, Vol. 68, No. 8, pp. 1159 – 1173, August 2019.
  50. M. G. Mankalale, Z. Zhao, J.-P. Wang, and S. S. Sapatnekar, "SkyLogic – A Proposal for a Skyrmion Logic Device," IEEE Transactions on Electron Devices, Vol. 66, No. 4, pp. 1990 – 1996, April 2019.
  51. F. S. Snigdha, D. Sengupta, J. Hu, and S. S. Sapatnekar, “Dynamic Approximation of JPEG Hardware,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 38, No. 2, pp. 295 – 308, February 2019.
  52. D. Sengupta, F. S. Snigdha, J. Hu, and S. S. Sapatnekar, “An Analytical Approach to Error PMF Characterization of Approximate Circuits,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 38, No. 1, pp. 70 – 83, January 2019.
  53. S. Marella and S. S. Sapatnekar, “Circuit Performance Shifts Due to Layout-Dependent Stress in Planar and 3D-ICs,” IEEE Transactions on VLSI Systems, Vol. 26, No. 12, pp. 2907–2920, December 2018.
  54. J. Song, I. Ahmed, Z. Zhao, D. Zhang, S. S. Sapatnekar, J.-P. Wang, and C. H. Kim, “Evaluation of Operating Margin and Switching Probability of Voltage Controlled Magnetic Anisotropy (VCMA) Magnetic Tunnel Junctions,” IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, Vol. 4, No. 2, pp. 76 – 84, December 2018.
  55. Z. Liang, M. G. Mankalale, J. Hu, Z. Zhao, J.-P. Wang, and S. S. Sapatnekar, “Performance Characterization and Majority Gate Design for MESO-based Circuits,” IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, Vol. 4, No. 2, pp. 51 – 59, December 2018.
  56. W. Xu, S. S. Sapatnekar, and J. Hu, “A Simple Yet Efficient Accuracy Configurable Adder Design,” IEEE Transactions on VLSI Systems, Vol. 26, No. 6, pp. 1112 – 1125, June 2018.
  57. Z. Chowdhury, J. D. Harms, S. K. Khatamifard, M. Zabihi, Y. Lv, A. P. Lyle, S. S. Sapatnekar, U. R. Karpuzcu, and J.-P. Wang, “Efficient In-Memory Processing Using Spintronics,” IEEE Computer Architecture Letters, Vol. 17, No. 1, pp. 42 – 46, January–June 2018.
  58. I. Ahmed, Z. Zhao, M. G. Mankalale, S. S. Sapatnekar, J.-P. Wang, and C. H. Kim, “A Comparative Study between Spin-Transfer-Torque (STT) and Spin-Hall-Effect (SHE) Switching Mechanisms using SPICE,” IEEE Journal on Exploratory Solid-State Computational Computational Devices and Circuits, Vol. 3, No. 1, pp. 74 – 82, December 2017.
  59. M. G. Mankalale, Z. Liang, Z. Zhao, C. H. Kim, J.-P.Wang, and S. S. Sapatnekar, “CoMET: Composite- Input Magnetoelectric-based Logic Technology,” IEEE Journal on Exploratory Solid-State Computational Computational Devices and Circuits, Vol. 3, pp. 27 – 36, December 2017.
  60. D. Sengupta and S. S. Sapatnekar, “Estimating Circuit Aging due to BTI and HCI using Ring-Oscillator- Based Sensors,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 36, No. 10, pp. 1688 – 1701, October 2017.
  61. P. Jain, V. Mishra, and S. S. Sapatnekar, “Fast Stochastic Analysis of Electromigration in Power Distribution Networks,” IEEE Transactions on VLSI Systems, Vol. 25, No. 9, pp. 2512 – 2524, September 2017.
  62. M. G. Mankalale, Z. Liang, and S. S. Sapatnekar, “STEM: A Scheme for Two-phase Evaluation of Majority Logic,” IEEE Transactions on Nanotechnology, Vol. 16, No. 4, pp. 1–10, July 2017.
  63. M. Mankalale and S. S. Sapatnekar, “Optimized Standard Cells for All-Spin Logic,” ACM Journal on Emerging Technology in Computing, Vol. 13, No. 2, pp. 21:1 – 21:22, November 2016.
  64. V. Mishra and S. S. Sapatnekar, “Probabilistic Wire Resistance Degradation due to Electromigration in Power Grids,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 36, No. 4, pp. 628 – 640, April 2017.
  65. Z. Liang and S. S. Sapatnekar, “Energy/Delay Tradeoffs in All-Spin Logic Circuits,” IEEE Journal on Exploratory Solid-State Computational Computational Devices and Circuits, Vol. 2, pp. 10 – 19, December 2016.
  66. P. Jain, J. Cortadella, and S. S. Sapatnekar, “A Fast and Retargetable Framework for Logic-IP-internal Electromigration Assessment Comprehending Advanced Waveform Effects,” IEEE Transactions on VLSI Systems, Vol. 24, No. 6, pp. 2345 – 2358, June 2016.
  67. G. Posser, V. Mishra, P. Jain, R. Reis, and S. S. Sapatnekar, “Cell-Internal Electromigration: Analysis and Pin Placement Based Optimization,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 35, No. 2, pp. 220 – 231, February 2016.
  68. J. Cortadella, M. Galceran-Oms, M. Kishinevsky, and S. S. Sapatnekar, “RTL Synthesis: From Logic Synthesis to Automatic Pipelining,” Proceedings of the IEEE, Vol. 103, No. 11, pp. 2061 – 2075, November 2015.
  69. S. Marella and S. S. Sapatnekar, “A Holistic Analysis of Circuit Performance Variations in 3D-ICs with Thermal and TSV-induced Stress Considerations,” IEEE Transactions on VLSI Systems, Vol. 23, No. 7, pp. 1308 – 1321, July 2015.
  70. J. Kim, A. Paul, P. A. Crowell, S. J. Koester, S. S.  Sapatnekar, J.-P. Wang, and C. H. Kim, “Spin Based Computing: Device Concepts, Current Status, and a Case Study on a High Performance Microprocessor,” Proceedings of the IEEE, Vol. 103, No. 1, pp. 106 – 130, January 2015.
  71. J. Fang and S. S. Sapatnekar, “Incorporating Hot Carrier Injection Effects into Timing Analysis for Large Circuits,” IEEE Transactions on VLSI Systems, Vol. 22, No. 5, pp. 2738 – 2751, December 2014.
  72. P. Zhou, A. Paul, C. H. Kim, and S. S. Sapatnekar, “Distributed On-Chip Switched-Capacitor DC-DC Converters Supporting DVFS in Multicore Systems,” IEEE Transactions on VLSI Systems, Vol. 22, No. 9, pp. 1954 – 1967, September 2014.
  73. B. Boghrati and S. S. Sapatnekar, “Incremental Analysis of Power Grids using Backward Random Walks,” ACM Transactions on Design Automation of Electronic Systems, Vol. 19, No. 3, pp. 31:1 – 31:29, June 2014.
  74. S. Gupta and S. S. Sapatnekar, “Variation-Aware Design of Variable Latency Units,” IEEE Transactions on VLSI Systems, Vol. 22, No. 5, pp. 1106 – 1117, May 2014.
  75. Y. Wei, C. Sze, N. Viswanathan, Z. Li, C. J. Alpert, L. Reddy, A. D. Huber, G. E. Tellez, D. Keller, and S. S. Sapatnekar, “Techniques for Scalable and Effective Routability Evaluation,” ACM Transactions on Design Automation of Electronic Systems, Vol. 19, No. 2, pp. 17:1 – 17:37, March 2014.
  76. S. Gupta and S. S. Sapatnekar, “Employing Circadian Rhythms to Enhance Power and Reliability,” ACM Transactions on Design Automation of Electronic Systems, Vol. 18, No. 3, pp. 38:1 – 38:23, July 2013.
  77. J. Fang and S. S. Sapatnekar, “The Impact of BTI Variations on Timing in Digital Logic Circuits,” IEEE Transactions on Device and Material Reliability, Vol.13, No. 1, pp. 277-286, March 2013.
  78. S. Gupta and S. S. Sapatnekar, “Compact Current Source Models for Timing Analysis under Temperature and Body Bias Variations,” IEEE Transactions on VLSI Systems, Vol. 20, No. 11, pp. 2104 – 2117, November 2012.
  79. J. Fang and S. S. Sapatnekar, “Scalable Methods for Analyzing the Circuit Failure Probability Due to Gate Oxide Breakdown,” IEEE Transactions on VLSI Systems, Vol. 20, No. 11, pp. 1960 – 1973, November 2012.
  80. H. Qian, S. S. Sapatnekar, and E. Kursun, “Fast Poisson Solvers for Thermal Analysis,” ACM Transactions on Design Automation of Electronic Systems, Vol. 17, No. 3, pp. 32:1 – 32:23, June 2012.
  81. J. Keane, C. H. Kim, Q. Liu, and S. S. Sapatnekar, “Process and Reliability Sensors for Nanoscale CMOS,” IEEE Design & Test, Vol. 29, No. 5, pp. 8 – 17, September/October 2012.
  82. P. Zhou, P.-H. Yuh, and S. S. Sapatnekar, “Optimized 3D Network-on-Chip Design Using Simulated Allocation,” ACM Transactions on Design Automation of Electronic Systems, Vol. 17, No. 2, pp. 12:1 – 12:19, April 2012.
  83. S. S. Sapatnekar, “Overcoming Variations in Nanometer-Scale Technologies,” IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Vol. 1, No. 1, pp. 5–18, March 2011.
  84. S. V. Kumar, C. H. Kim, and S. S. Sapatnekar, “Adaptive Techniques for Overcoming Performance Degradation due to Aging in CMOS Circuits,” IEEE Transactions on VLSI Systems, Vol. 19, No. 4, pp. 603–614, January 2011.
  85. Q. Liu and S. S. Sapatnekar, “Capturing Post-Silicon Variations using a Representative Critical Path,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 29, No. 2, pp. 211 – 222, February 2010.
  86. S. V. Kumar, C. H. Kim, and S. S. Sapatnekar, “A Finite Oxide Thickness Based Analytical Model for Negative Temperature Bias Instability,” IEEE Transactions on Device and Material Reliability, Vol. 9, No. 4, pp. 537 – 556, December 2009.
  87. P. Zhou, K. Sridharan, and S. S. Sapatnekar, “Power Grid Optimization in 3D Circuits Using MIM and CMOS Decoupling Capacitors,” IEEE Design & Test, Vol. 26, No. 5, pp. 15 – 25, 2009.
  88. P.-H. Yuh, S. S. Sapatnekar, C.-L. Yang, and Y.-W. Chang, “A Progressive-ILP Based Routing Algorithm for the Synthesis of Cross-Referencing Biochips,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 28, No. 9, pp. 1295 – 1306, September 2009.
  89. Q. Liu and S. S. Sapatnekar, “A Framework for Scalable Post-Silicon Statistical Delay Prediction under Spatial Variations,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 28, No. 8, pp. 1201 – 1212, August 2009.
  90. H. D. Mogal, H. Qian, S. S. Sapatnekar, and K. Bazargan, “Fast and Accurate Statistical Criticality Computation under Process Variations,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 28, No. 3, pp. 350 – 363, March 2009.
  91. Y. Zhan, S. V. Kumar, and S. S. Sapatnekar, “Thermally-Aware Design,” Foundations and Trends in Electronic Design Automation, Vol. 2, No. 3, pp. 255 – 370, 2008.
  92. Y. Zhan and S. S. Sapatnekar, “Automated Module Assignment in Stacked-Vdd Designs for High-Efficiency Power Delivery,” ACM Journal on Emerging Technologies in Computing Systems, Vol. 4, No. 4, pp. 18:1 – 18:20, October 2008.
  93. S. S. Sapatnekar, “Variability and Statistical Design,” IPSJ Transactions on System LSI Design Methodology, Vol. 1, pp. 18 – 32, August 2008.
  94. J. Keane, H. Eom, T.-H. Kim, S. Sapatnekar, and C. Kim, “Stack Sizing for Optimal Current Drivability in Subthreshold Circuits,” IEEE Transactions on VLSI Systems, Vol. 16, No. 5, pp. 598 – 602, May 2008.
  95. H. Qian and S. S. Sapatnekar, “Stochastic Preconditioning for Diagonally Dominant Matrices,” SIAM Journal on Scientific Computing, Vol. 30, No. 3, pp. 1178 – 1204, March 2008.
  96. S. V. Kumar, C. H. Kim, and S. S. Sapatnekar, “Body Bias Voltage Computations for Process and Temperature Compensation,” IEEE Transactions on VLSI Systems, Vol. 16, No. 3, pp. 249 – 262, March 2008.
  97. T. Zhang and S. S. Sapatnekar, “Buffering Global Interconnects in Structured ASIC Design,” Integration: The VLSI Journal, Vol. 41, No. 2, pp. 171 – 182, February 2008.
  98. J. Gu, J. Keane, S. S. Sapatnekar, and C. H. Kim, “Statistical Leakage Estimation of Double Gate FinFET Devices Considering the Width Quantization Property,” IEEE Transactions on VLSI Systems, Vol. 16, No. 2, pp. 206 – 209, February 2008.
  99. J. Singh, Z.-Q. Luo, and S. Sapatnekar, “A Geometric Programming-based Worst-Case Gate Sizing Method Incorporating Spatial Correlation,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 27, No. 2, pp. 295 – 308, February 2008.
  100. J. Singh and S. S. Sapatnekar, “A Scalable Statistical Static Timing Analyzer Incorporating Correlated Non-Gaussian and Gaussian Parameter Variations,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 27, No. 1, pp. 160 – 173, January 2008.
  101. S. K. Karandikar and S. S. Sapatnekar, “Technology Mapping Using Logical Effort Solving the Load Distribution Problem,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 27, No. 1, pp. 45 – 48, January 2008.
  102. Y. Zhan and S. S. Sapatnekar, “High Efficiency Green Function-Based Thermal Simulation Algorithms,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 26, No. 9, pp. 1661 – 1675, September 2007.
  103. T. Zhang and S. S. Sapatnekar, “Simultaneous Shield and Buffer Insertion for Crosstalk Noise Reduction in Global Routing,” IEEE Transactions on VLSI Systems, Vol. 15, No. 6, pp. 624 – 636, June 2007.
  104. H. Chang and S. S. Sapatnekar, “Prediction of Leakage Power under Process Uncertainties,” ACM Transactions on Design Automation of Electronic Systems, Vol. 12, No. 2, pp. 12:1 – 12:27, April 2007.
  105. J.-L. Tsai, C. C.-P. Chen, G. Chen, B. Goplen, H. Qian, Y. Zhan, S.-M. Kang, D.-F. Wong, and S. S. Sapatnekar, “Temperature-Aware Placement for SOCs,” Proceedings of the IEEE, Vol. 94, No. 8, pp. 1502 - 1518, August 2006.
  106. C. J. Alpert, J. Hu, S. S. Sapatnekar, and C. N. Sze, “Accurate Estimation of Global Buffer Delay within a Floorplan,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 25, No. 6, pp. 1140 – 1146, June 2006.
  107. R. S. Shelar, P. Saxena, and S. S. Sapatnekar, “Technology Mapping Targeting Routing Congestion Under Delay Constraints,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 25, No. 4, pp. 625 – 636, April 2006.
  108. J. Singh and S. S. Sapatnekar, “A Partition-based Algorithm for Power Grid Design using Locality,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 25, No. 4, pp. 664 – 677, April 2006.
  109. B. Goplen and S. S. Sapatnekar, “Placement of Thermal Vias in 3D ICs using Various Thermal Objectives,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 25, No. 4, pp. 692 – 709, April 2006.
  110. S. K. Karandikar and S. S. Sapatnekar, “Fast Comparisons of Circuit Implementations,” IEEE Transactions on VLSI Systems, Vol. 13, No. 12, pp. 1329 – 1339, December 2005.
  111. A. K. Sultania, D. Sylvester, and S. S. Sapatnekar, “Gate Oxide Leakage and Delay Tradeoffs for Dual Tox Circuits,” IEEE Transactions on VLSI Systems, Vol. 13, No. 12, pp. 1362 – 1375, December 2005.
  112. C. Ababei, Y. Feng, B. Goplen, H. Mogal, T. Zhang, K. Bazargan, and S. S. Sapatnekar, “Placement and Routing in 3D Integrated Circuits,” IEEE Design & Test of Computers, Vol. 22, No. 6, pp. 520 – 531, Nov – Dec 2005.
  113. H. Chang and S. S. Sapatnekar, “Statistical Timing Analysis Under Spatial Correlations,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 24, No. 9, pp. 1467 – 1482, September 2005.
  114. R. S. Shelar and S. S. Sapatnekar, “BDD Decomposition for Delay Oriented Pass Transistor Logic Synthesis,” IEEE Transactions on VLSI Systems, Vol. 13, No. 8, pp. 957 – 970, August 2005.
  115. H. Qian, S. R. Nassif, and S. S. Sapatnekar, “Power Grid Analysis using Random Walks,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 24, No. 8, pp. 1204 – 1224, August 2005.
  116. R. S. Shelar, S. S. Sapatnekar, P. Saxena, and X. Wang, “A Predictive Distributed Congestion Metric with Appication to Technology Mapping,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 24, No. 5, pp. 696 – 710, May 2005.
  117. J. Singh and S. S. Sapatnekar, “Congestion-Aware Topology Optimization of Structured Power/Ground Networks,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 24, No. 5, pp. 683 – 695, May 2005.
  118. H. Qian, S. R. Nassif, and S. S. Sapatnekar, “Early-stage Power Grid Analysis for Uncertain Working Modes,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 24, No. 5, pp. 676 – 682, May 2005.
  119. H. Su, J. Hu, S. S. Sapatnekar, and S. R. Nassif, “A Methodology for the Simultaneous Design of Supply and Signal Networks,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 23, No. 12, pp. 1614 – 1624, December 2004.
  120. V. Sundararajan, S. S. Sapatnekar, and K. K. Parhi, “A New Approach for Integration of Min-Area Retiming and Min-Delay Padding for Simultaneously Addressing Short-path and Long-path Constraints,” ACM Transactions on Design Automation of Electronic Systems, Vol. 9, No. 3, pp. 273 – 289, July 2004.
  121. S. K. Karandikar and S. S. Sapatnekar, “Technology Mapping for SOI Domino Logic Incorporating Solutions for the Parasitic Bipolar Effect,” IEEE Transactions on VLSI Systems, Vol. 11, No. 9, pp. 1094 – 1105, December 2003.
  122. H. Su, K. Gala, and S. S. Sapatnekar, “Analysis and Optimization of Structured Power/Ground Networks,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 22, No. 11, pp. 1533 – 1544, November 2003.
  123. S. S. Sapatnekar and H. Su, “Analysis and Optimization of Power Grids,” IEEE Design and Test (Special Issue on Power Supply and Analysis for IC's), Vol. 20, No. 3, pp. 7 – 15, May-June 2002.
  124. C. J. Alpert, J. Hu, S. S. Sapatnekar, and P. Villarrubia, “A Practical Methodology for Early Buffer and Wire Resource Allocation,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 22, No. 5, pp. 573 – 583, May 2003.
  125. H. Su, S. S. Sapatnekar, and S. R. Nassif, “Optimal Decoupling Capacitor Sizing and Placement for Standard Cell Layout Designs,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 22, No. 4, pp. 428 – 436, April 2003.
  126. H. Hu, D. T. Blaauw, V. Zolotov, K. Gala, M. Zhao, R. Panda, and S. S. Sapatnekar, “Fast On-Chip Inductance Simulation using a Precorrected-FFT Method,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 22, No. 1, pp. 49 – 61, January 2003.
  127. H. Hu and S. S. Sapatnekar, “Efficient Inductance Extraction using Circuit-Aware Techniques,” IEEE Transactions on VLSI Systems, Vol. 10, No. 6, pp. 746 – 761, December 2002.
  128. J. Hu and S. S. Sapatnekar, “A Timing-constrained Simultaneous Global Routing Algorithm,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 21, No. 9, pp. 1025 – 1036, September 2002.
  129. J. Pangjun and S. S. Sapatnekar, “Low Power Clock Distribution using Multiple Voltages and Reduced Swings,” IEEE Transactions on VLSI Systems, Vol. 10, No. 3, pp. 309 – 318, June 2002.
  130. J. Hu and S. S. Sapatnekar, “Performance Driven Global Routing Through Gradual Refinement,” VLSI Design (Special Issue on Timing Analysis and Optimization for Deep Sub-Micron ICs), Vol. 15, No. 3, pp. 595 – 604, 2002.
  131. V. Sundararajan, S. S. Sapatnekar, and K. K. Parhi, “Fast and Exact Transistor Sizing Based on Iterative Relaxation,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 21, No. 5, pp. 568 – 581, May 2002.
  132. S. Raman, S. S. Sapatnekar, and C. J. Alpert, “Probability-driven Routing in a Datapath Environment,” Integration: The VLSI Journal, Vol. 31, No. 2, pp. 159 – 182, May 2002.
  133. M. Zhao and S. S. Sapatnekar, “Technology Mapping Algorithms for Domino Logic,” ACM Transactions on Design Automation of Electronic Systems, Vol. 7, No. 2, pp. 306 – 335, April 2002.
  134. M. Zhao, R. V. Panda, S. S. Sapatnekar, and D. T. Blaauw, “Hierarchical Analysis of Power Distribution Networks,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 21, No. 2, pp. 159 – 168, Feb 2002.
  135. C. J. Alpert, M. Hrkic, J. Hu, A. B. Kahng, J. Lillis, B. Liu, S. T. Quay, S. S. Sapatnekar, A. J. Sullivan, and P. Villarubia, “Buffered Steiner Trees for Difficult Instances,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 21, No. 1, pp. 3 – 14, Jan 2002.
  136. J. Hu and S. S. Sapatnekar, “A Survey on Multi-net Global Routing for Integrated Circuits,” Integration: The VLSI Journal, Vol. 31, No. 1, pp. 1 – 49, November 2001.
  137. Y. Jiang, S. S. Sapatnekar and C. Bamji, “Technology Mapping for High Performance Static CMOS and Pass Transistor Logic Designs,” IEEE Transactions on VLSI Systems, Vol. 9, No. 5, pp. 577 – 589, October 2001.
  138. M. Kuhlmann and S. S. Sapatnekar, “Exact and Efficient Crosstalk Estimation,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 20, No. 7, pp. 858 – 866, July 2001.
  139. C. J. Alpert, G. Gandham, J. Hu, J. L. Neves, S. T. Quay and S. S. Sapatnekar, “A Steiner Tree Construction for Buffers, Blockages and Bays,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 20, No. 4, pp. 556 – 562, April 2001.
  140. M. Zhao and S. S. Sapatnekar, “Timing-driven Partitioning and Timing Optimization of Mixed Static-Domino Implementations,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 19, No. 11, pp. 1322 – 1336, November 2000.
  141. K. Kasamsetty, M. Ketkar, and S. S. Sapatnekar, “A New Class of Convex Functions for Delay Modeling and their Application to the Transistor Sizing Problem,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 19, No. 7, pp. 779 – 788, July 2000.
  142. S. S. Sapatnekar, “A Timing Model Incorporating the Effect of Crosstalk on Delay and its Application to Optimal Channel Routing,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 19, No. 5, pp. 550 – 559, May 2000.
  143. J. Hu and S. S. Sapatnekar, “Algorithms for Non-Hanan-based Optimization for VLSI Interconnect under a Higher Order AWE Model,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 19, No. 4, pp. 446 – 458, April 2000.
  144. S. S. Sapatnekar and W. Chuang, “Power-Delay Optimizations in Gate Sizing,” ACM Transactions on Design Automation of Electronic Systems, Vol. 5, No. 1, pp. 98 – 114, January 2000.
  145. N. Maheshwari and S. S. Sapatnekar, “Optimizing Large Multiphase Level-Clocked Circuits,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 18, No. 9, pp. 1249 – 1264, September 1999.
  146. N. Maheshwari and S. S. Sapatnekar, “Retiming Control Logic,” Integration: The VLSI Journal, Vol. 28, No. 1, pp. 33 – 53, September 1999.
  147. H. Hou, J. Hu and S. S. Sapatnekar, “NonHanan Routing,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 18, No. 4, pp. 436 – 444, April 1999.
  148. Y. Jiang, S. S. Sapatnekar, C. Bamji and J. Kim, “Interleaving Buffer Insertion and Transistor Sizing into a Single Optimization,” IEEE Transactions on VLSI Systems, Vol. 6, No. 4, pp. 625 – 633, December 1998.
  149. J. C. Shah, A. A. Younis, S. S. Sapatnekar, and M. M. Hassoun, “An Algorithm for Simulating Power/Ground Networks using Padé Approximants and its Symbolic Implementation,” IEEE Transactions on Circuits and Systems II, Vol. 45, No. 10, pp. 1372 – 1382, October 1998.
  150. N. Maheshwari and S. S. Sapatnekar, “Efficient Retiming of Large Circuits,” IEEE Transactions on VLSI Systems, Vol. 6, No. 1, pp. 74 – 83, March 1998.
  151. H. Sathyamurthy, S. S. Sapatnekar, and J. P. Fishburn, “Speeding up Pipelined Circuits through a Combination of Gate Sizing and Clock Skew Optimization,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 17, No. 2, pp. 173 – 182, February 1998.
  152. D. Lehther and S. S. Sapatnekar, “Moment-Based Techniques for RLC Clock Tree Construction,” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, Vol. 45, No. 1, pp. 69 – 79, January 1998.
  153. S. Ramaswamy, S. Sapatnekar, and P. Banerjee, “A Framework for Exploiting Data and Functional Parallelism on Distributed Memory Multicomputers,” IEEE Transactions on Parallel and Distributed Systems. Vol. 8, No. 11, pp. 1098 – 1116, November 1997.
  154. S. S. Sapatnekar and R. B. Deokar, “Utilizing the Retiming-Skew Equivalence in a Practical Algorithm for Retiming Large Circuits,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. Vol. 15, No. 10, pp. 1237 – 1248, October 1996.
  155. P. K. Sancheti and S. S. Sapatnekar, “Optimal Design of Macrocells for Low Power and High Speed,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. Vol. 15, No. 9, pp. 1160 – 1166, September 1996.
  156. S. S. Sapatnekar, “Wire Sizing as a Convex Optimization Problem: Exploring the Area Delay Tradeoff,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 15, No. 8, pp. 1001 – 1011, August 1996.
  157. W. Chuang, S. S. Sapatnekar, and I. N. Hajj, “Timing and Area Optimization for Standard-Cell VLSI Circuit Design,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 14, No. 3, pp. 308 – 320, March 1995.
  158. S. S. Sapatnekar, P. M. Vaidya, and S. M. Kang, “Convexity-based Algorithms for Design Centering,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 13, No. 12, pp. 1536 – 1549, December 1994.
  159. S. S. Sapatnekar, V. B. Rao, P. M. Vaidya, and S. M. Kang, “An Exact Solution to the Transistor Sizing Problem for CMOS Circuits using Convex Optimization,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 12, No. 11, pp. 1621 – 1634, November 1993.
  160. S. S. Sapatnekar and V. B. Rao, “A Transistor Sizing Tool for CMOS Circuits,” Journal of Semicustom IC's, Vol. 8, No. 2, pp. 39 – 44, 1990.